1. Field of the Invention
The present invention relates to a random access memory (to be referred to as a RAM hereinafter) mounted on a semiconductor substrate and, more particularly, to a read/write control circuit for use in an asynchronous RAM whose operating state is uniquely defined by the states of signals input to a chip.
2. Description of the Related Art
As an asynchronous RAM of this type, an asynchronous static RAM using static memory cells is available.
FIG. 1 is a circuit diagram showing a conventional asynchronous static RAM. This static RAM will be described below as a 4-bit RAM. Static RAM cells 11 to 14 are connected bit lines BL1, BL1, BL2, and BL2 and word lines WL1 and WL2. A bit line load circuit 15 and a column selecting circuit 16 are connected to the bit lines BL1, BL1, BL2, and BL2, and Address signals A0 and A1 are supplied to input pins 17 and 18. Each of these input pins 17 and 18 is connected to one input terminal of a corresponding one of NOR circuits 19 and 20. The output terminal of the NOR circuit 19 is connected to a row decoder 21 for decoding the address signals A0 and A1 and selecting the word lines WL1 and WL2. The output terminal of the NOR circuit 20 is connected to a column decoder 22 for decoding the address signals A0 and A1 and selecting the bit lines BL1, BL1, BL2, and BL2 through the column selecting circuit 16. The output terminals of a write buffer 23 and the input terminals of a sense amplifier 24 are connected to the column selecting circuit 16. The write buffer 23 serves to write data in selected one of the static RAM cells 11 to 14. The sense amplifier 24 serves to amplify data read out from selected one of the static RAM cells 11 to 14. An input pin 25, to which input data Din is input, is connected to one input terminal of the write buffer 23. The output terminal of the sense amplifier 24 is connected to the first input terminal of an output buffer 27 through an inverter circuit 26. The output terminal of the output buffer 27 is connected to an output pin 28 for outputting output data Dout. A chip select signal CS is supplied to an input pin 29. This input pin 29 is connected to the other input terminal of each of the NOR circuits 19 and 20 through inverter circuits 30 and 31, and is also connected to one input terminal of each of NOR circuits 32 and 33. In addition, a read/write signal R/W is supplied to an input pin 34. This input pin 34 is connected to both the other input terminal of the NOR circuit 32 and the other input terminal of the NOR circuit 33. The NOR circuit 33 serves to generate an output enable signal OE. The output terminal of the NOR circuit 33 is connected to the second input terminal of the output buffer 27. Furthermore, the output terminal of the NOR circuit 32 is connected to the other input terminal of the write buffer 23 and a gate circuit 23a.
In the above-described arrangement, when the memory is set in the read mode, data read out from a selected memory cell is supplied to the sense amplifier 24 through corresponding bit lines and the column selecting circuit 16. The data is amplified by the sense amplifier 24 and is subsequently output from the output pin 28 through the output buffer 27. When the memory is set in the write mode, the input data Din input through the input pin 25 is written in a selected memory cell. The read and write modes of the memory are switched in accordance with the read/write signal R/W supplied to the input pin 34. More specifically, if the read/write signal R/W is "1", the read mode is set to activate the sense amplifier 24 and the output buffer 27. In contrast to this, if the read/write signal R/W is "0", the write mode is set to activate the write buffer 23. The above-described read/write operation is performed only when the chip select signal CS is "0". When the chip select signal CS is "1", the memory is set in the standby mode. The operating state of the asynchronous static RAM is uniquely determined by the states of the read/write signal R/W, the chip select signal CS, and an address signal but is not influenced by the past history. Therefore, the asynchronous static RAM can be easily controlled and used and can be operated at high speed.
Although the operating state of the asynchronous static RAM is uniquely determined by signals supplied to the input pin, it must be guaranteed that the RAM is operated according to the values designated by the specifications regardless of the timing at which signals are input. For this reason, in a RAM of this type, it is difficult to guarantee predetermined performance especially associated with a read/write mode switching operation. More specifically, consider a write recovery time T.sub.WR shown in FIG. 2A as one of specifications of such a RAM. Referring to FIG. 2A, reference symbol T.sub.WP denotes a write time; and T.sub.AS, a setup time. The write recovery time T.sub.WR defines the time difference between the time at which the write mode is switched to the read mode, i.e., the read/write signal R/W supplied to the input pin 34 changes from "0" to 37 0", and the time at which an address signal Add changes. As the write recovery time T.sub.WR is closer to "0" second, as shown in FIG. 2B, switching to a read operation of data defined by the next address can be performed at a higher speed after the write operation is completed, thus allowing an increase in operating frequency. If, however, the write recovery time T.sub.WR is set to be close to "0" second, a write operation may be completed before the next address is selected. As a result, a read time delay may be caused. In the worst case, the write recovery time T.sub.WR becomes a negative value to destroy data in a memory cell.
In order to ensure the write recovery time T.sub.WR designated by the specifications, the following method may be used. The threshold voltage of a logic gate constituted by the inverters and the like in the write buffer 23, to which the read/write signal R/W is supplied, is set beforehand to a level at which a change in the read/write signal R/W from "0" to "1" can be easily detected. With this method, the write recovery time T.sub.WR can be set to be close to "0" second. In the above-described method, however, the timing at which the read mode is switched to the write mode is delayed, and hence the timing at which a data write operation is started is delayed. For this reason, the minimum write time T.sub.WP designated by the specifications cannot be ensured.